The U.S. patent of Small, U.S. Pat. No. 4,554,229, granted Nov. 19, 1985, describes a multilayer hybrid integrated circuit comprising photodefinable polymer dielectric layers. Such layers can be formed over a conductor pattern and then patterned by selective exposure to actinic light and development. Microvia holes in the dielectric may, for example, be formed, which are then used to permit interconnection of a conductor pattern on the upper surface of the dielectric layer with the conductor pattern it overlies. Multiple layers can be successively formed in this manner with each interconnection pattern being used to interconnect a number of semiconductor chips. The overall structure may constitute, for example, a multilayer hybrid integrated circuit, multichip module (MCM), or other packages which can provide high density interconnection of a number of complex chips with relatively low loss.
One problem with the dielectric of the Small patent is that it is susceptible to cracking when subjected to temperature extremes. This problem becomes more severe as density requirements dictate an increase in the number of layers. For example, a four layer test circuit may show signs of cracks after fifty temperature cycles of from -40.degree. C. to 150.degree. C. It would also be desirable to increase the resolution with which the photodefinable dielectric film responds to actinic light.